Analog-digital converter

ABSTRACT

An integrator consisting of a high gain D.C. amplifier, a voltage-current converter such as a resistor, and a feed-back capacitor. An unknown analog input voltage to be converted and two known reference analog voltages which have the same polarity as that of the input voltage to be converted are supplied to the voltage-current converter in the integrator through a first switching circuit having three switches. The output voltage of the integrator is supplied to a comparator. The comparator compares the integrated voltage with a fixed reference voltage and produces an output signal when both voltages are equal. A second switching circuit including one switch, a third switching circuit including two switches, and two capacitors respectively connected to the switches in the third switching circuit are provided between an output terminal of the integrator and ground. A voltage-current converter such as a resistor or a transistor circuit is connected between the input terminal of the D.C. amplifier and the interconnecting point of the second and third switching circuits. Each switch in the first, second and third switching circuits, is controlled by a switch control circuit. The switch control circuit includes counters, flip-flops, calculating circuits and delay circuits. A voltage corresponding to one of the two known reference voltages is stored in one of the two capacitors connected to the ground and a voltage corresponding to the other known reference voltage is stored in the other capacitor connected to the ground. A combined voltage of the input voltage and the voltage stored in one of the two capacitors and a combined voltage of one of the reference voltages and the voltage stored in the other capacitor are respectively integrated by the integrator. As a result thereof, a digital quantity representative of the ratio of the unknown input voltage and the difference between the two reference voltages is obtained by the switch control circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to an analog-digital converter whichuses a dual-slope method, and more particularly, to an analog-digitalconverter in which two known reference voltages whose polarities are thesame as that of the unknown input voltage to be converted are used asthe input voltages to the integrator.

2. Description of the Prior Art

An analog-digital converter which uses a dual-slope method is known.This kind of converter basically comprises an integrator, a comparator,switching circuits and a switch control circuit. The integrator furtherincludes a D.C. amplifier, an input resistor and a feed-back capacitoras shown in FIG. 1.

In this kind of converter, a known analog reference voltage having apolarity opposite to that of the analog input voltage to be converted isused as one of the input voltages to the integrator.

In FIG. 1, the analog input voltage to be converted V_(s) is supplied toan input terminal 1a and analog reference voltage -V_(r) whose polarityis opposite to that of the input voltage V_(s) is supplied to an inputterminal 1b.

At first, the input terminal 1a is connected to a terminal 3 in theswitch circuit 2 according to the output signal from a switching controlcircuit 9. As a result thereof, the input voltage V_(s) is integrated bythe integrator 4 consisting of the D.C. amplifier 5, the input resistor6 and the feed-back capacitor 7.

The comparator 8 compares the level of the integrated voltage V_(o) withthe level of a fixed reference voltage V_(c) . After the input voltageV_(s) is supplied to the amplifier 5 for the period T₁ , the switchingcontrol circuit 9 generates a signal to the switching circuit 2 and theinput terminal 1b is connected to the terminal 3. As a result thereof,the reference voltage -V_(r) is integrated by the integrator 4.

FIG. 2 shows an integrated voltage V_(o) . In FIG. 2, T₂ is the periodin which the reference voltage -V_(r) is supplied to the integrator 4.T₁ is a predetermined period and T₂ is a period measured in the switchcontrol circuit 9.

In this case, if the D.C. amplifier 5 has not offset, the followingrelative equation is applicable ##EQU1##

T₁ and T₂ are measured by counting the clock pulses in the switchingcontrol circuit 9. Consequently, the ratio V_(s) /V_(r) can be obtainedas the ratio T₂ /T₁ and the digital quantity of the analog voltage V_(s)may be obtained.

However, the D.C. amplifier 5 generally has an offset. Therefore, theabove relative equation is not applicable. Instead, the followingrelative equation is applicable ##EQU2## where Δ V is the offset voltageof the D.C. amplifier 5.

Consequently, the ratio V_(s) /V_(r) cannot be obtained as the ratio T₂/T₁ .

Therefore, manual adjustment of the D.C. amplifier 5 is necessary tocompensate for ΔV. Moreover, it is necessary to carry out azero-adjustment and a full-scale adjustment everytime prior to actualmeasurement because the offset voltage ΔV varies as a result of thetemperature or as a result of other circumstances.

In order to automatically compensate for the offset voltage ΔV thefollowing method has been suggested. Namely, as shown in FIG. 3, aserial connection circuit of switching circuit 11 and capacitor 12 isprovided between the output terminal of the integrator 4 and the ground,and the interconnecting point of the serial circuit is connected to agate terminal of a field-effect transistor (FET) 13. And further, asource terminal of the FET 13 is connected to a terminal 14 in theswitching circuit 2.

In this construction, at first, the terminal 14 is connected to theterminal 3 and the switching circuit 11 is closed. As a result thereof,the current ΔV/R flows through the input resistor 6 and the feed-backcapacitor 7 is charged. When the circuit assumes its stationary state,the voltage level of an input terminal 15 of the D.C. amplifier 5 andthe level of the source terminal of the FET 13 are equal to each other.Therefore, current does not flow through the input resistor 6. Underthis situation, the voltage level of the source terminal of the FET 13is equal to -ΔV.

Subsequently, the switching circuit 11 is opened and a terminal 16 isconnected to the terminal 3 by the output signal from the switchingcontrol circuit 9. Therefore, the voltage (V_(s) -ΔV) is integrated bythe integrator 4.

This integration operation is continued for the period T₁ . After that,the terminal 17 is connected to the terminal 3 and then the voltage(-V_(r) -ΔV) is integrated. This integration operation is continueduntil the comparator 8 generates the output signal.

In this case, the following relative equation is applicable.

    (V.sub.s -Δ V+ Δ U) T.sub.1 + (-V.sub.r -Δ V+ Δ V) T.sub.2 = 0

where T₂ is the period in which the voltage (- V_(r) -Δ V) isintegrated.

Therefore, the following relative equation can be obtained. ##EQU3##

This method shows that the opposite polarity voltage -ΔV is previouslyobtained and, in the actual measuring operation, the combined voltage ofV_(s) and -ΔV or -V_(r) and -ΔV in integrated.

Consequently, according to this method, the zero-adjustment andfull-scale-adjustment are automatically carried out.

In the above-mentioned prior art, however, it is necessary that thepolarities of the converted voltage V_(s) and standard voltage -V_(r) beopposite each other. Generally, two voltage sources are required inorder to obtain two voltages of different polarities. In this case, itis quite difficult to maintain the two voltages at predetermined levels.Further, the abberations of the two voltages have a direct effect uponthe digital quantities of the converted voltage even though the D.C.amplifier does not have the offset.

Furthermore, even when two voltages of opposite polarity are obtainedfrom one voltage source, it is quite difficult to maintain the voltagesat predetermined levels because of the abberration generated by thepolarity converter, which abberration directly affects the accuracy ofthe A-D conversion.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a newand improved analog-digital converter.

Another object of the present invention is to provide a new and improvedanalog-digital converter in which two standard analog voltages havingpolarities the same as that of a voltage to be converted are used.

Briefly, according to the invention, an unknown analog voltage to beconverted and two known analog reference voltages having the samepolarity as that of the unknown analog voltage to be converted aresupplied to an integrator including a D.C. amplifier through a firstswitching circuit.

In order to maintain the voltages corresponding to the respectivereference voltages, a second switching circuit, a third switchingcircuit and two capacitors are provided.

In the actual measuring operation, a combined voltage of the voltage tobe converted and the voltage maintained in one of the two capacitors anda combined voltage of one of the reference voltages and the voltagemaintained in the other of the capacitors are integrated by theintegrator.

BRIEF DESCRIPTION OF THE DRAWINGS

Various objects, features and attendant advantages of the presentinvention will be more fully appreciated as the same becomes betterunderstood from the following detailed description of the presentinvention when considered in connection with the accompanying drawings,in which:

FIG. 1 is a diagram showing a fundamental circuit of an analog-digitalconverter using the dual-slope method;

FIG. 2 is a diagram showing an output voltage of the integrator in FIG.1;

FIG. 3 is a diagram showing another prior analog-digital convertercircuit;

FIG. 4 is a diagram showing a preferred embodiment of an analog-digitalconverter in accordance with the present invention;

FIG. 5A is a diagram showing an integrated voltage in accordance withthe present invention;

FIG. 5B is a diagram showing the status of each switch in the presentinvention;

FIG. 6 is a diagram showing the details of a switching control circuitin the present invention; and

FIG. 7 is a diagram showing another embodiment of an analog-digitalconverter in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the drawings, wherein like reference numerals designateidentical or corresponding parts throughout the several views, and moreparticularly to FIG. 4 thereof, the preferred embodiment of the presentinvention is diagrammatically illustrated in FIG. 4.

In FIG. 4, two reference voltages V_(H) and V_(L) are respectivelysupplied to input terminals 41a and 41b and an unknown voltage to beconverted V_(s) is supplied to an input terminal 41c. The polarity ofthe two reference voltages V_(H) and V_(L) and the voltage V_(S) are thesame. The level of V_(S) is selected between the levels of V_(H) andV_(L) . Thus, the relation among the three voltages is V_(H) >V_(S)>V_(L) .

The operation of this converter is described as follows with referenceto FIGS. 4, 5A and 5B.

At first, at the time t= t₀ , a switch SW₁ in the first switchingcircuit 42, a switch SW₄ in the second switching circuit 43 and a switchSW₅ in the third switching circuit 44 are respectively closed. As aresult thereof, the reference voltage V_(H) is supplied to an integrator45 having a D.C. amplifier 46, a voltage-current converter such as aresistor 47 and a feed-back capacitor 48. The D.C. amplifier 46 has highamplification. A reference voltage V_(B) supplied to the positive inputterminal of the D.C. amplifier 46 has a value selected between V_(H) andV_(L) . This condition is continued until the circuit assumes itsstationary state.

When the circuit assumes its stationary state, the current i_(C1)flowing in the feed-back capacitor 48 is equal to zero and the followingrelative equation is applicable

    i.sub.2 = i.sub.1 + i.sub.3

where i₂ is the current which flows in a voltage-current converter 49having a resistor and a buffer circuit connected between the negativeinput terminal of the D.C. amplifier 46 and the third switching circuit44; i₁ is the current which flows in the V-I converter 47; and, i₃ isthe offset current of the D.C. amplifier 46.

On the assumption that i₁ is equal to i_(1V).sbsb.h and i₂ is equal toi_(2V).sbsb.H , the above relative equation should be changed asfollows:

    i.sub.2V.sbsb.H = i.sub.1V.sbsb.h + i.sub.3

In this state, the voltage corresponding to the output voltage V_(O)(which is assumed to be V_(OV).sbsb.H) of the D.C. amplifier 46 ischarged in a capacitor 50a connected between the switch SW₅ and theground. The level of the voltage V_(OV).sbsb.h is lower than the levelof the voltage V_(C) supplied to one of the input terminals of acomparator 51 as shown in FIG. 5A.

At the time t=t₁, a switch SW₂ in the first switching circuit 42, aswitch SW₄ in the second switching circuit 43 and a switch SW₆ in thethird switching circuit 44 are closed. As a result thereof, thereference voltage V_(L) is supplied to the integrator 45. This conditionis continued until the circuit assumes its stationary state.

When the circuit assumes its stationary state, the following relativeequation is applicable

    i.sub.2V.sbsb.l =i.sub.1V.sbsb.l + i.sub.3

where i_(2V).sbsb.l is the current i₂ in the period when V_(L) isintegrated; and, i_(1V).sbsb.l is the current i₁ in the period whenV_(L) is integrated.

In this state, the voltage corresponding to the output voltage V_(O)(Which is assumed to be V_(OV).sbsb.l) of the D.C. amplifier 46 ischarged in capacitor 50b connected between the switch SW₆ and theground. The level of the voltage V_(OV).sbsb.l is higher than the levelof the voltage V_(C) as shown in FIG. 5A. Namely, the voltage V_(C) isselected between the levels of V_(OV).sbsb.l and V_(OV).sbsb.h.

At the time t=t₂, the switch SW₄ in the second switching circuit 43 isopened, and the switch SW₃ in the first switching circuit 42 and theswitch SW₆ in the third switching circuit 44 are closed. As a resultthereof, a combined voltage V_(S) and the voltage stored in condenser50b is supplied to the integrator 45.

In this state, the current I₂ is i_(2V).sbsb.l (= i_(1V).sbsb.l + i₃).Therefore, assuming that the present current i₁ is i_(1V).sbsb.s, thefollowing relative equation is obtained.

    I.sub.C1 =i.sub.2V.sbsb.l -i.sub.1V.sbsb.s -i.sub.3 = i.sub.1V.sbsb.l - i.sub.1V.sbsb.s                                           (1)

therefore, the output voltage V_(O) of the integrator 45 decreaseslinearly as shown in FIG. 5A and the output voltage V_(O) of theintegrator 45 at the time t=t₄ is as follows:

    V.sub.O (t=t.sub.4)= C.sub.1 (i.sub.1V.sbsb.l -i.sub.1V.sbsb.s) T.sub.1 + V.sub. O(t=t.sbsb.3)                                      (2)

where C₁ is the capacity of the feed-back capacitor 48; V.sub.O(t=t.sbsb.3 ) is the output voltage level of the D.C. amplifier 46 atthe time t=t₃, and is equal to V_(C) which is supplied to the comparator51; and, T₁ is the period from t=t₃ to t=t₄.

Subsequently, at the time t=t₄, the switch SW₂ in the first switchingcircuit 42 and the switch SW₅ in the third switching circuit 44 areclosed. As a result thereof, a combined voltage of reference voltageV_(L) and the voltage stored in the capacitor 50a is supplied to theintegrator 45.

In this state, the current i₂ is i_(2V).sbsb.h (= i_(1V).sbsb.h + i₃)and the voltage V_(OV).sbsb.h is stored in the condenser 50a. Therefore,the current i_(c1), which flows in the feed-back capacitor 48, is asfollows,

    I.sub.C1 = i.sub.2V.sbsb.h -i.sub.1V.sbsb.l -i.sub.3       (3)

Therefore, the output voltage V_(O) of the integrator 45 increaseslinearly as shown in FIG. 5A.

At the time t=t₅, the output voltage V_(O) of the integrator 45 is asfollows:

    V.sub. O(t.sub.= t.sbsb.5 ) = C.sub.1 (i.sub.1V.sbsb.h -i.sub.1V.sbsb.L)T.sub.2 + V.sub. O(t.sub.=t.sbsb.4)      (4)

where V.sub. O(t_(=t).sbsb.4 ) is the output voltage level of the D.C.amplifier 46 at the time t=t₄ ; V_(O)(t_(=t).sbsb.5) is equal to V.sub.O(t_(=t).sbsb.3), and is also equal to V_(C) ; and, T₂ is the periodfrom t=t₄ to t=t₅.

Consequently, the following relative equation is obtained from equations(2) and (4). ##EQU4## where ##EQU5##

Therefore, finally, the following relative equation is applicable.##EQU6##

In equations (6) and (7), T₁ is a predetermined period and T₂ may beobtained by measurement. Therefore, it is possible to obtain the digitalquantities of the voltage V_(S) as the ratio T₂ /I₁.

It is to be understood that the offset current or offset voltage of theD.C. amplifier 45 does not effect the digital quantities obtained by theconverter of the present invention.

The operation of the switches SW₁, SW₂, SW₃, SW₄, SW₅ and SW₆ arerespectively controlled by a switch control circuit 52. The digitalquantities of the voltage V_(S) are obtained by the switching controlcircuit 52.

The details of the switching control circuit 52 are as follows.

FIG. 6 shows a diagram of the switching control circuit 52. In thecircuit shown in FIG. 6, all counters 61, 62, 63 and 64 and a calculator65 are cleared by a clear pulse generated by a manual-clear terminal 66.This clear pulse is also supplied to a delay circuit 67. The circuit 67delays passing the clear pulse for an appropriate period.

The signal generated by the delay circuit 67 is supplied to the setterminals of a flip-flop 68 and the counters 61 and 62.

As a result thereof, a Q-terminal of the flip-flop 68 generates anoutput signal "1" and the counters 61 and 62 start counting the clockpulse transferred from a clock-pulse generator 69. The output signalgenerated by the flip-flop 68 is supplied to switches SW₁, SW₄ and SW₅in order to close these switches.

After the predetermined period, the counter 61 generates an outputsignal. At this moment, the counter 62 is still continuing the countingoperation. The moment at which the counter 61 generates the outputsignal corresponds to the time t=t₁.

The output signal of the counter 61 is supplied to the reset terminal ofthe flip-flop 68 and to the set terminal of a flip-flop 70. As a resultthereof, the switches SW₁ and SW₅ are opened and the switches SW₂, SW₄and SW₆ are closed.

After the predetermined period, the counter 62 produces an outputsignal. The moment at which the counter 62 generates the output signalcorresponds to the time t=t₂.

As a result of the output signal being generated by the counter 62, theflip-flop 70 is reset and a flip-flop 71 is set. Consequently, theswitches SW₂ and SW₄ are opened and the switches SW₃ and SW₆ are closed.

The period of the count operation of the counters 61 and 62 may berespectively determined on the basis of the stability of the circuit.

As a result of the switches SW₃ and Sw₆ being closed, the output voltageV_(O) of the integrator 45 linearly decreases as shown in FIG. 5A.

At the time t=t₃, a signal generated by the comparator 51 is supplied toan AND gate 72. Therefore, the AND gate 72 supplies an output signal toa set terminal of the counter 63, and the counter 63 starts the countoperation.

After the counter 63 counts the clock pulses for the period T₁, thecounter 63 generates an output signal. The flip-flop 71 is reset and aflip-flop 73 is set by the output signal produced from the counter 63.The time at which the counter 63 supplies the output signal correspondsto the time t=t₄.

As a result thereof the switches SW₃ and SW₆ are opened and the switchesSW₂ and SW₅ are closed. At this moment, the output voltage V_(O) of theintegrator 45 starts increasing as shown in FIG. 5A.

The output signal of the counter 63 is also supplied to the counter 64as a set signal. Therefore, the counter 64 starts to count the clockpulses.

At the time t=t₅, the comparator 51 generates an output signal. Thisoutput signal is supplied to a reset terminal of the flip-flop 73 and tothe calculator 65 through an AND gate 74. Consequently, the counter 64transfers the contents therein (or the count number showing the periodT₂) to the calculator 65.

The calculator 65 comprises certain registers including a register inwhich the digital quantities corresponding to the term T₁ areregistered. The calculator 65 further comprises an operating circuit forthe four fundamental rules of arithmetic.

The digital quantities of the voltage V_(S) are obtained by thecalculator 65 on the basis of the afore-mentioned relative equation (7).

A delay circuit 75 delays the output signal of the AND gate 74 for anappropriate period and then generates an output signal. This outputsignal is supplied to the counters 61, 62, 63 and 64, to the calculator65 and to the delay circuit 67 as a clear pulse.

After the clear pulse is supplied to the delay circuit 67, the switchcontrol circuit 52 may automatically repeat the operation in the samemanner as mentioned above.

According to the present invention, as mentioned above, the unknownvoltage to be converted V_(S) and two known reference voltages V_(H) andV_(L) having the same polarity as that of the voltage V_(S) are suppliedto the integrator 45. The voltage corresponding to the integratedvoltages V_(H) and V_(L) are respectively stored in the capacitors 50aand 50b. In the actual-measuring operation, the combined voltage of thevoltage corresponding to the voltage V_(OV).sbsb.l and the voltage V_(S)is integrated for the predetermined period T₁. After that, the combinedvoltage of the voltage corresponding to the voltage V_(OV).sbsb.h andthe voltage V_(L) is supplied to the integrator 45 in order to obtainthe period T₂.

Therefore, it is possible to secure three voltages V_(S), V_(H) andV_(L) from one voltage source. Furthermore, the polarity-converter isnot required in the present invention. Therefore it is clear that notonly does the aberration caused by the offset of the D.C amplifier notaffect the quantities of the A-D conversion, but, the aberrations of thereference voltage are of no consequence.

Further, it is obvious that the zero adjustment and thefull-scale-adjustment are automatically effected in the same manner asthe apparatus shown in FIG. 3.

Furthermore, the reference voltages V_(B) and V_(C) respectivelysupplied to the D.C. amplifier 46 and the comparator 51 may be of thesame polarity as that of the voltages V_(S), V_(H) and V_(L).

Consequently, it is possible to operate the converter of the presentinvention using only one voltage source. As a result thereof, converterminiaturization can be realized.

FIG. 7 shows another preferred embodiment of the present inventionwherein like reference numerals refer to or designate identical orcorresponding parts as that shown in FIG. 4.

In this arrangement, a switching circuit 80 is provided between theoutput terminal of the D.C. amplifier 46 and the input terminal of thecomparator 51. A switch SW₇ in the switching circuit 80 is opened forthe period from t=t₀ to t=t₂ by the output signal produced from theswitching control circuit 52. As a result thereof, the period from themoment when the reference voltages V_(H) and V_(L) are supplied to theD.C. amplifier 46 to the moment when the circuit assumes its stationarystate is easily abbreviated.

It is believed clear that the switching circuit 80 does not affect theresult of the A-D conversion even if the switch SW₇ has a conductiveresistance.

The above explanation has been for the case when the level of thevoltage to be converted V_(S) is between the level of the referencevoltage V_(H) and the level of the reference voltage V_(L). However, theoperation of the converter of the present invention need not necessarilybe so related to the levels of these three voltages.

For example, in the case when the level of the voltage V_(S) is higherthan that of the reference voltage V_(H), the decreasing gradient of theintegrated voltage V_(O) should be steeper during the period from t=t₂to t=t₄.

In FIGS. 4 and 7, the V-I converters 47 and 49 may be replaced withresistors. All switches SW₁, SW₂, SW₃, SW₄, SW₅ SW₆ and SW₇ may beelectrical, electronic or mechanical switches. In FIG. 6, all countersmay be replaced with at least one register.

Obviously, numerous modifications and variations of the presentinvention are possible in light of the above teachings. It is thereforeto be understood that within the scope of the appended claims, theinvention may be practiced otherwise than as specifically describedherein.

What is claimed as new and desired to be secured by Letters Patent ofthe United States is:
 1. An analog-digital converter comprising:a D.C.amplifier; a first voltage-current converter connected to an inputterminal of the D.C. amplifier, a feed-back capacitor connected betweenthe input terminal of the D.C. amplifier and an output terminal of theD.C. amplifier, a first switching circuit for supplying an unknownanalog voltage to be converted and first and second analog referencevoltages having the same polarity as that of the converted voltage tothe first voltage-current converter, a serial connection circuit of asecond switching circuit and a second voltage-current converterconnected between the output terminal of the D.C. amplifier and theinput terminal of the D.C. amplifier, a third switchng circuit havingtwo switches with one of the switches being connected to aninter-connecting point of the serial connection circuit; a firstcapacitor connected between one of the two switches in the thirdswitching circuit and ground to maintain a first voltage correspondingto an output voltage of the D.C. amplifier in the period when only thefirst reference voltage is supplied to the D.C. amplifier, a secondcapacitor connected between one of the switches in the third switchingcircuit and ground to maintain a second voltage corresponding to anoutput voltage of the D.C. amplifier during the period when only thesecond reference voltage is supplied to the D.C. amplifier, a comparatorfor producing an output signal when the levels of the output voltage ofthe D.C. amplifier are equal to the level of a reference voltage and aswitch control circuit for controlling the first, second and thirdswitching circuits to maintain the first and second voltagescorresponding to the output voltages of the D.C. amplifier respectivelyin the first and second capacitors, to supply a first combined voltageof the second voltage corresponding to the output voltage of the D.C.amplifier and the unknown analog voltage to be converted to the D.C.amplifier for a predetermined period, to supply a second combinedvoltage of the first voltage corresponding to the output voltage of theD.C. amplifier and the second reference voltage to the D.C. amplifierand to obtain a digital quantity of the unknown analog voltage to beconverted by measuring the period in which the second combined voltageis supplied to the D.C. amplifier.
 2. An analog-digital converteraccording to claim 1 wherein the first voltage-current converter is aresistor.
 3. An analog-digital converter according to claim 1 whereinthe second voltage-current converter comprises a resistor and a buffercircuit.
 4. An analog-digital converter according to claim 1 wherein theswitches in the first, second and third switching circuits areelectronic switches.
 5. An analog-digital converter according to claim 1wherein said switch control circuit comprises:a clock-pulse generator, afirst counter for determining the end of the period during which onlythe first reference voltage is supplied to the D.C. amplifier bycounting a clock pulse generated by the clock-pulse generator, a secondcounter for determining the end of the period during which only thesecond reference voltage is supplied to the D.C. amplifier by counting aclock pulse generated by the clock-pulse generator. a third counter forcounting a clock pulse generated by the clock-pulse generator for apredetermined period after the comparator generates an output signalwhen a combined voltage of the unknown analog voltage to be convertedand a voltage stored in the second capacitor is supplied to the D.C.amplifier, and a fourth counter for measuring the period after acombined voltage of the second reference voltage and a voltage stored inthe first capacitor is supplied to the D.C. amplifier until thecomparator generates an output signal by a counting a clock pulsegenerated from the clock-pulse generator.
 6. An analog-digital converteraccording to claim 5 wherein the switch control circuit furthercomprises a calculator for obtaining a digital quantity of the unknownanalog voltage to be converted on the basis of an output signalgenerated by the fourth counter.
 7. An analog-digital converteraccording to claim 5 wherein the switch control circuit furthercomprises a delay circuit for automatically clearing the first, second,third and fourth counters and the calculator.
 8. An analog-digitalconverter comprising:a D.C. amplifier; a first voltage-current converterconnected to an input terminal of the D.C. amplifier, a first switchingcircuit for supplying an unknown analog voltage to be converted andfirst and second analog reference voltages having the same polarity asthat of the converted voltage to the first voltage-current converter, aserial connection circuit of a second switching circuit and a secondvoltage-current converter connected between the output terminal of theD.C. amplifier and the input terminal of the D.C. amplifier, a thirdswitching circuit having two switches with one of the switches beingconnected to an inter-connecting point of the serial connection circuit;a first capacitor connected between one of the two switches in the thirdswitching circuit and ground to maintain a first voltage correspondingto an output voltage of the D.C. amplifier in the period when only thefirst reference voltage is supplied to the D.C. amplifier, a secondcapacitor connected between one of the switches in the third switchingcircuit and ground to maintain a second voltage corresponding to anoutput voltage of the D.C. amplifier during the period when only thesecond reference voltage is supplied to the D.C. amplifier, a comparatorfor producing an output signal when the levels of the output voltage ofthe D.C. amplifier are equal to the level of a reference voltage, afourth switching circuit connected between the input terminal of thecomparator and an output terminal of the D.C. amplifier, a feed-backcapacitor connected between the input terminal of the D.C. amplifier andthe input terminal of the comparator, and a switch control circuit forcontrolling the first, second and third switching circuits to maintainthe first and second voltages corresponding to the output voltages ofthe D.C. amplifier respectively in the first and second capacitors, tosupply a first combined voltage of the second voltage corresponding tothe output voltage of the D.C. amplifier and the unknown analog voltageto be converted to the D.C. amplifier for a predetermined period, tosupply a second combined voltage of the first voltage corresponding tothe output voltage of the D.C. amplifier and the second referencevoltage to the D.C. amplifier and to obtain a digital quantity of theunknown analog voltage to be converted by measuring the period in whichthe second combined voltage is supplied to the D.C. amplifier.